畢業(yè)設(shè)計(jì) 基于FPGA的直接數(shù)字頻率合成器的設(shè)計(jì)

摘 要
  在頻率合成領(lǐng)域，常用的頻率合成技術(shù)有直接模擬合成、模擬鎖相環(huán)、小數(shù)分頻鎖相環(huán)等，直接數(shù)字頻率合成（Direct Digital Frequency Synthesis ，DDFS，簡(jiǎn)稱DDS）是近年來(lái)的新的頻率合成技術(shù)。DDS以穩(wěn)定度高的參考時(shí)鐘為參考源，通過(guò)精密的相位累加器和數(shù)字信號(hào)處理，再通過(guò)高速D/A變換器產(chǎn)生所需的數(shù)字波形，這個(gè)數(shù)字波形經(jīng)過(guò)一個(gè)模擬濾波器后，得到最終的模擬信號(hào)波形。DDS是產(chǎn)生高精度、快速頻率變換、輸出波形失真小的優(yōu)先選用技術(shù)。
本文介紹了直接數(shù)字頻率合成器的基本組成及設(shè)計(jì)原理，給出了基于FPGA的具體設(shè)計(jì)方案及編程實(shí)現(xiàn)方法。本設(shè)計(jì)中DDS主要由相位累加寄存器、微控制接口、雙端口RAM等三個(gè)部分組成。仿真結(jié)果表明，該設(shè)計(jì)簡(jiǎn)單合理，使用靈活方便，通用性好，可寫入各種FPGA芯片。同時(shí)，由于FPGA現(xiàn)場(chǎng)可編程，設(shè)計(jì)復(fù)雜或者簡(jiǎn)單系統(tǒng)完全從實(shí)際需要出發(fā)，通過(guò)重寫RAM/ROM數(shù)據(jù)，可以做到任意波形輸出和動(dòng)態(tài)波形輸出，這是其他方法所無(wú)法比擬的?；贔PGA的直接數(shù)字頻率合成設(shè)計(jì)方法，在利用比例乘法器時(shí)，可將頻率分辨率提高到驚人的程度。因此，DDS廣泛應(yīng)用于電子測(cè)量、調(diào)頻通信、電子對(duì)抗等領(lǐng)域。
關(guān)鍵詞： 直接數(shù)字頻率合成器(DDS)，VHDL，現(xiàn)場(chǎng)可編程門陣列(FPGA) 

Abstract
In Frequency domain, the common Synthesis technology has Direct simulation, phase lock loop simulation, decimal Frequency and phase lock loop, Direct Digital Frequency Synthesis (Direct Digital Frequency Synthesis,DDFS,for short DDS) in recent years is the new Frequency Synthesis technology. With high stability of DDS reference clock for reference source, through the precise phase accumulator and digital signal processing, again through high-speed D/A converter for digital waveform, through a filter, the digital waveform finally is converted to simulation signal waveform. Because of high precision , fast conversion of frequency and the little distortion of waveform , DDS is becoming the better choice.
The paper introduces the basic direct digital frequency synthesizer design principle, and gives the specific design scheme based on FPGA and programming method. The DDS in this paper is mainly made up by phase accumulate registers, micro control interface and two-port RAM . Simulation results show that the design is simple and reasonable, use agile and convenient, generality, writeable various FPGA chip. Because the FPGA could be programmed directly, when design complicated or simple system completely from the actual need, through rewriting RAM/ROM data, DDS can output any kinds of waveform ,aslo dynamic waveform. which is other methods can not get. This chapter is proposed based on FPGA digital frequency direct synthesis utilization ratio, and the design method of frequency resolution on time-multiplier, will increase to an alarming extent. So it is wdely used in electronic measurement ,spurious frequency modulation communication, electronic counter, and so on.
Key words： Direct Digital frequency Synthesizer(DDS)，VHDL，
Field－Programmable Gate Array (FPGA)

目錄
1  前言 1
   1.1 課題背景 1
   1.2 課題目的和意義 2
   1.3 DDS發(fā)展前景 2
2  設(shè)計(jì)開(kāi)發(fā)環(huán)境概述 4
   2.1 FPGA 4
      2.1.1  FPGA工作原理 4
      2.1.2  FPGA的應(yīng)用 5
   2.2 VHDL 6
      2.2.1  VHDL系統(tǒng)設(shè)計(jì)的特點(diǎn) 7
      2.2.2  VHDL系統(tǒng)優(yōu)勢(shì) 8
   2.3 Quartus II簡(jiǎn)介 9
3  各種頻率合成技術(shù) 10
   3.1 直接模擬（DAS） 10
   3.2 間接式頻率合成（PLL） 10
   3.3 直接數(shù)字頻率合成（DDS） 11
4  系統(tǒng)設(shè)計(jì) 15
   4.1 模塊劃分 15
      4.1.1  微控制器接口模塊 16
      4.1.2  相位累加寄存器 16
      4.1.3  雙端口RAM 16
   4.2 各功能模塊設(shè)計(jì)與實(shí)現(xiàn) 17
      4.2.1  微控制器接口模塊 17
      4.2.2  比例乘法器模塊 21
      4.2.3  相位累加器模塊 27
      4.2.4  雙端口RAM模塊 27
   4.3 頂層模塊綜合仿真 33
5  結(jié)論 36
致謝 37
參考文獻(xiàn) 38
附錄 39