基于FPGACPLD的FIR數(shù)字濾波器設(shè)計



摘  要


隨著電子技術(shù)、計算機技術(shù)和信息科學(xué)的迅速發(fā)展，信號的數(shù)字處理方法已經(jīng)成為信號與信息處理的主要手段。與此同時，大量非線性電子器件的引入，電網(wǎng)中的諧波污染日益嚴(yán)重，對電力諧波加以監(jiān)測和限制變得尤為迫切。無論是模擬濾波還是數(shù)字濾波，其目的都是為了壓制輸入信號的某些頻率成分，從而改變信號頻譜中各頻率分量的相對比例。數(shù)字濾波作為數(shù)字信號處理技術(shù)的重要組成部分，較之傳統(tǒng)的由R、L、C元件和運算放大器組成的模擬濾波器有著無可比擬的優(yōu)勢，因而廣泛應(yīng)用于信號分離、恢復(fù)、整形等場合。

FIR濾波器，即有限長單位沖激響應(yīng)濾波器，是數(shù)字信號處理系統(tǒng)中最基本的元件，它可以在保證任意幅頻特性的同時具有嚴(yán)格的線性相頻特性，并且其單位抽樣響應(yīng)是有限長的，因此得到廣泛應(yīng)用。而現(xiàn)場可編程邏輯門陣列（FPGA）以其可編程性，低成本性，高邏輯密度和高可靠性，得到了越來越廣泛的應(yīng)用，對于研究數(shù)字濾波器有相當(dāng)重要的意義。結(jié)合數(shù)字濾波器的基本理論及基于FPGA的實現(xiàn)方法，利用MATLAB和QUARTUS Ⅱ仿真軟件設(shè)計FIR數(shù)字濾波器，并對其進行仿真。

關(guān)鍵詞：數(shù)字信號處理；數(shù)字濾波器；FIR；FPGA


 


 


 


 


 


 




Abstract


With the rapid development of electronic technology, computer technology and information science，digital signal processing methods have become the main means to process signal and information. At the same time, because of the introduction of a large number of non-linear electronic devices, harmonic pollution in power increases seriously, so the power to monitor and limit harmonics becomes more urgent. No matter analog filtering or digital filtering, the aim is to suppress certain frequency components of the input signal, then to change the signal spectrum in the relative proportions of the various frequency components. Digital filter regarding as an important part of digital signal processing technology, comparing with traditional analog filters composed by the R, L, C elements and the operational amplifier has an unparalleled advantage ,which is widely used in signal separation, recovery, plastic and other occasions.

FIR filter, called the finite impulse response filter, is the most basic components of digital signal processing system. It can ensure any amplitude-frequency characteristics and a strictly linear phase frequency characteristics, and its unit sample response is finite length, therefore it is widely used. Field programmable gate array (FPGA) with its programmability, low-cost, high logic density and high reliability, application has been more and more extensive, which makes considerable importance for the study of digital filter. Combining the basic theory with digital filter realization method based on FPGA, we use MATLAB and QUARTUS Ⅱ simulation software to design FIR digital filter, then simulate.

Keywords: Digital signal processing; digital filter; FIR; FPGA


 




 

目  錄


引  言 1

第一章 緒論 2

1.1 課題研究意義 2

1.2 國內(nèi)外研究現(xiàn)狀 3

1.3 本論文所作工作 3

第二章 數(shù)字濾波器 4

2.1數(shù)字濾波器簡述 4

2.2 數(shù)字濾波器的結(jié)構(gòu)表示法 4

2.3 FIR數(shù)字濾波器基本理論 5

2.4 FIR數(shù)字濾波器的結(jié)構(gòu) 6

2.5 FIR數(shù)字濾波器的設(shè)計方法 9

2.5.1窗函數(shù)設(shè)計線性相位FIR濾波器的基本方法 9

2.5.2 幾種窗函數(shù)及窗函數(shù)選擇原則 10

2.6  FIR濾波器的特點 11

第三章 FIR濾波器的MATLAB設(shè)計 13

3.1 MATLAB設(shè)計方法 13

3.1.1 FIR數(shù)字濾波器的直接程序設(shè)計法 13

3.1.2 利用FDATool界面的設(shè)計法 13

3.2 利用FDATool界面設(shè)計FIR數(shù)字濾波器方法 14

3.2.1 FIR濾波器的設(shè)計要求及參數(shù)選取 14

3.2.2 FDATool設(shè)計法操作流程 14

第四章 基于FPGA的FIR數(shù)字濾波器的實現(xiàn) 19

4.1 FPGA簡介 19

4.1.1 FPGA的結(jié)構(gòu)和工作原理 19

4.1.2 FPGA與CPLD的聯(lián)系與區(qū)別 20

4.2 編程環(huán)境Quartus Ⅱ和器件介紹 21

4.2.1 Quartus Ⅱ簡明介紹 22

4.2.2 Cyclone Ⅱ器件介紹 22

4.2.3 EP2C5F256C8芯片簡介 24

4.3 程序設(shè)計 25

4.3.1 對稱型FIR濾波器設(shè)計程序 25

4.3.2 加法樹乘法器程序 31

4.3.3 頂層文件的設(shè)計 33

4.3.4 輸出結(jié)果分析 33

4.4 FIR濾波器的仿真 34

4.5 結(jié)果誤差分析 35

結(jié)  論 37

參考文獻 38

謝  辭 39