碩士畢業(yè)論文 現(xiàn)場可編程門陣列(fpga)模擬電路設(shè)計研究.rar
碩士畢業(yè)論文 現(xiàn)場可編程門陣列(fpga)模擬電路設(shè)計研究,摘要fpga是英文field programmable gate array的縮寫，即現(xiàn)場可編程門陣列，是在pal、gal、epld等可編程器件基礎(chǔ)上進一步發(fā)展的產(chǎn)物。作為專用集成電路(asic)領(lǐng)域中的一種半定制電路產(chǎn)品，該產(chǎn)品既解決了定制電路的不足，又避免了原有可編程器件門電路資源有限的缺點。隨著工藝尺寸的逐漸減小...
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摘 要
FPGA是英文Field Programmable Gate Array的縮寫，即現(xiàn)場可編程門陣列，是在PAL、GAL、EPLD等可編程器件基礎(chǔ)上進一步發(fā)展的產(chǎn)物。作為專用集成電路(ASIC)領(lǐng)域中的一種半定制電路產(chǎn)品，該產(chǎn)品既解決了定制電路的不足，又避免了原有可編程器件門電路資源有限的缺點。隨著工藝尺寸的逐漸減小，現(xiàn)場可編程門陣列FPGA與專用集成電路ASIC之間的性能差異正在逐漸減小。相比較ASIC而言，由于FPGA 的動態(tài)可重配置特性極大降低了電路設(shè)計公司在產(chǎn)品設(shè)計過程中的設(shè)計風險與設(shè)計成本，縮短了產(chǎn)品上市的時間，減少了用戶升級系統(tǒng)所帶來的硬件花費。因此，越來越多的電路設(shè)計公司開始逐漸使用FPGA作為產(chǎn)品研發(fā)與測試的硬件平臺。
本課題來源為總裝備部國防技術(shù)重點預研項目和國家863研究發(fā)展計劃中“可編程邏輯器件”課題的子項目。課題的目的是研究工作電壓為2.5 V 的FPGA芯片中模擬電路的設(shè)計方法，其研究范圍主要包括I/O接口電路和FPGA芯片的電源模塊。本課題打破了FPGA核心關(guān)鍵設(shè)計技術(shù)和產(chǎn)品制造被國外公司所壟斷的不利局面，滿足了國防和工業(yè)生產(chǎn)的需要。
本論文采用正向和逆向相結(jié)合的設(shè)計方法，以正向設(shè)計思想為指導方向，同時借鑒國外先進的設(shè)計經(jīng)驗，以研制支持多達16種高性能接口標準的可動態(tài)配置I/O端口，最高工作頻率為200MHz，可用邏輯資源為10萬門，內(nèi)部包含總量達40K的用戶可用RAM陣列，消耗晶體管個數(shù)為530萬的現(xiàn)場可編程門陣列FPGA芯片為突破口，完成了可用I/O管腳資源為180、404和512的系列FPGA產(chǎn)品模擬電路的設(shè)計。其中I/O管腳資源為180的FPGA產(chǎn)品具有小于4.8ns的輸入延時和小于4.0ns的輸出延遲，并能夠滿足FPGA芯片200MHz的最高工作頻率。
本文中的電路采用TSMC 0.22um 1P5M標準CMOS工藝制程，使用全定制電路與版圖設(shè)計方法。經(jīng)仿真驗證，該系列FPGA產(chǎn)品所達到的主要技術(shù)參數(shù)指標，均優(yōu)于國外同類產(chǎn)品水平。
本文的主要創(chuàng)新點為利用SRAM技術(shù)的在系統(tǒng)可編程特性，結(jié)合模擬電路設(shè)計方法的特點，提供了一種能夠同時滿足多標準接口應(yīng)用與可動態(tài)配置要求的I/O接口電路結(jié)構(gòu)。該結(jié)構(gòu)相比過去的各種I/O接口電路結(jié)構(gòu)而言，不但節(jié)約了芯片面積，而且能夠支持多種不同的接口標準。
本文所設(shè)計的多標準高性能接口電路已應(yīng)用在采用陶瓷封裝形式的FPGA中，該產(chǎn)品解決了國外同類型產(chǎn)品沒有軍品級器件的問題，滿足重點軍事工程的需求。
本文所設(shè)計的電路已完成后端版圖設(shè)計與仿真驗證，目前處于流片階段，其他系列產(chǎn)品的設(shè)計均按型譜項目的進度要求正在進行中。該系列產(chǎn)品的研制成功打破了國外對該系列器件的禁運，為我軍關(guān)鍵電子元器件的國產(chǎn)化貢獻了力量。
關(guān)鍵詞：FPGA 可動態(tài)配置I/O 多標準 5V容許 Weak-Keeper
ABSTRACT
FPGA was the abbreviation of the Field Programmable Gate Array .It was base on the programmable divices ,such as PAL and EPLD.It offset the ASIC's disadvantage whose logic resouce was too less.With the character size smaller and smaller ,the distance of performance between FPGA and ASIC was smaller and smaller.But FPGA decreased the risk and cost in the product design, for its character of the dynamic reuse ,and shorten the time which the product come into the market.And more and more Fabless began to use it as the design and test platform.
This research subject came from Hi-Tech Research and Development Program of China and General Equipment Headquarters. It aimed at developing series products of 2.5v FPGA, including I/O interface circuit and power system, breaking through the adverse situation as all of the FPGA products and design technology were monopolized by several American companies, and satisfying urgent demands of national defence.
A method of “top-down” design and reverse design was adopted in this paper. We took the idea of “top-down” design as guidance, as well as used foreign advanced design experience for reference and developed a FPGA containing 20*30 CLB-arrays, an internal counter of 200MHz, 100K gates，supporting 16 high-performance interface standards as a breakthrough, a series of FPGA family products, whose maximum available I/O number is 180 , 404 and 512, have been developed respectively. The 180-I/O FPGA has a 4.8ns pin-to-pin input delay and 4.0ns pin-to-pin output delay or less.
This paper was based on a 0.22um 1P5M standard CMOS technology process, and on a design technology of custom layout. The primary technology parameters of the FPGA family products accomplish the foreign advanced level of kindred products.
New idea of our research subject was a new I/O cicuit structure by using the SRAM array design to realize in-system programmable and the characters of analog cicuit design.This structure can reduce the chip area and give higher performance.
The 180-I/O FPGA chip with ceramic packages solved the problem that there were no military devices in foreign kindred products and satisfied the requirement of important military engineering.
This product has been finished the layout design.Other designs of the FPGA series were completed and were ahead of the schedule of plan. The products were used and approbated by many customer, we broke the forbiddance for the devices by foreign countries, and contributed that the key device can be established in China for our army.
Keywords: FPGA Dynamic-configuration I/O Multi-standards 5V-tolerance Weak-keeper
目 錄
第一章 緒 論 1
1.1 課題的背景和意義 1
1.1.1 現(xiàn)場可編程門陣列簡介 2
1.1.2 SRAM編程技術(shù)介紹 3
1.1.3 FPGA..
FPGA是英文Field Programmable Gate Array的縮寫，即現(xiàn)場可編程門陣列，是在PAL、GAL、EPLD等可編程器件基礎(chǔ)上進一步發(fā)展的產(chǎn)物。作為專用集成電路(ASIC)領(lǐng)域中的一種半定制電路產(chǎn)品，該產(chǎn)品既解決了定制電路的不足，又避免了原有可編程器件門電路資源有限的缺點。隨著工藝尺寸的逐漸減小，現(xiàn)場可編程門陣列FPGA與專用集成電路ASIC之間的性能差異正在逐漸減小。相比較ASIC而言，由于FPGA 的動態(tài)可重配置特性極大降低了電路設(shè)計公司在產(chǎn)品設(shè)計過程中的設(shè)計風險與設(shè)計成本，縮短了產(chǎn)品上市的時間，減少了用戶升級系統(tǒng)所帶來的硬件花費。因此，越來越多的電路設(shè)計公司開始逐漸使用FPGA作為產(chǎn)品研發(fā)與測試的硬件平臺。
本課題來源為總裝備部國防技術(shù)重點預研項目和國家863研究發(fā)展計劃中“可編程邏輯器件”課題的子項目。課題的目的是研究工作電壓為2.5 V 的FPGA芯片中模擬電路的設(shè)計方法，其研究范圍主要包括I/O接口電路和FPGA芯片的電源模塊。本課題打破了FPGA核心關(guān)鍵設(shè)計技術(shù)和產(chǎn)品制造被國外公司所壟斷的不利局面，滿足了國防和工業(yè)生產(chǎn)的需要。
本論文采用正向和逆向相結(jié)合的設(shè)計方法，以正向設(shè)計思想為指導方向，同時借鑒國外先進的設(shè)計經(jīng)驗，以研制支持多達16種高性能接口標準的可動態(tài)配置I/O端口，最高工作頻率為200MHz，可用邏輯資源為10萬門，內(nèi)部包含總量達40K的用戶可用RAM陣列，消耗晶體管個數(shù)為530萬的現(xiàn)場可編程門陣列FPGA芯片為突破口，完成了可用I/O管腳資源為180、404和512的系列FPGA產(chǎn)品模擬電路的設(shè)計。其中I/O管腳資源為180的FPGA產(chǎn)品具有小于4.8ns的輸入延時和小于4.0ns的輸出延遲，并能夠滿足FPGA芯片200MHz的最高工作頻率。
本文中的電路采用TSMC 0.22um 1P5M標準CMOS工藝制程，使用全定制電路與版圖設(shè)計方法。經(jīng)仿真驗證，該系列FPGA產(chǎn)品所達到的主要技術(shù)參數(shù)指標，均優(yōu)于國外同類產(chǎn)品水平。
本文的主要創(chuàng)新點為利用SRAM技術(shù)的在系統(tǒng)可編程特性，結(jié)合模擬電路設(shè)計方法的特點，提供了一種能夠同時滿足多標準接口應(yīng)用與可動態(tài)配置要求的I/O接口電路結(jié)構(gòu)。該結(jié)構(gòu)相比過去的各種I/O接口電路結(jié)構(gòu)而言，不但節(jié)約了芯片面積，而且能夠支持多種不同的接口標準。
本文所設(shè)計的多標準高性能接口電路已應(yīng)用在采用陶瓷封裝形式的FPGA中，該產(chǎn)品解決了國外同類型產(chǎn)品沒有軍品級器件的問題，滿足重點軍事工程的需求。
本文所設(shè)計的電路已完成后端版圖設(shè)計與仿真驗證，目前處于流片階段，其他系列產(chǎn)品的設(shè)計均按型譜項目的進度要求正在進行中。該系列產(chǎn)品的研制成功打破了國外對該系列器件的禁運，為我軍關(guān)鍵電子元器件的國產(chǎn)化貢獻了力量。
關(guān)鍵詞：FPGA 可動態(tài)配置I/O 多標準 5V容許 Weak-Keeper
ABSTRACT
FPGA was the abbreviation of the Field Programmable Gate Array .It was base on the programmable divices ,such as PAL and EPLD.It offset the ASIC's disadvantage whose logic resouce was too less.With the character size smaller and smaller ,the distance of performance between FPGA and ASIC was smaller and smaller.But FPGA decreased the risk and cost in the product design, for its character of the dynamic reuse ,and shorten the time which the product come into the market.And more and more Fabless began to use it as the design and test platform.
This research subject came from Hi-Tech Research and Development Program of China and General Equipment Headquarters. It aimed at developing series products of 2.5v FPGA, including I/O interface circuit and power system, breaking through the adverse situation as all of the FPGA products and design technology were monopolized by several American companies, and satisfying urgent demands of national defence.
A method of “top-down” design and reverse design was adopted in this paper. We took the idea of “top-down” design as guidance, as well as used foreign advanced design experience for reference and developed a FPGA containing 20*30 CLB-arrays, an internal counter of 200MHz, 100K gates，supporting 16 high-performance interface standards as a breakthrough, a series of FPGA family products, whose maximum available I/O number is 180 , 404 and 512, have been developed respectively. The 180-I/O FPGA has a 4.8ns pin-to-pin input delay and 4.0ns pin-to-pin output delay or less.
This paper was based on a 0.22um 1P5M standard CMOS technology process, and on a design technology of custom layout. The primary technology parameters of the FPGA family products accomplish the foreign advanced level of kindred products.
New idea of our research subject was a new I/O cicuit structure by using the SRAM array design to realize in-system programmable and the characters of analog cicuit design.This structure can reduce the chip area and give higher performance.
The 180-I/O FPGA chip with ceramic packages solved the problem that there were no military devices in foreign kindred products and satisfied the requirement of important military engineering.
This product has been finished the layout design.Other designs of the FPGA series were completed and were ahead of the schedule of plan. The products were used and approbated by many customer, we broke the forbiddance for the devices by foreign countries, and contributed that the key device can be established in China for our army.
Keywords: FPGA Dynamic-configuration I/O Multi-standards 5V-tolerance Weak-keeper
目 錄
第一章 緒 論 1
1.1 課題的背景和意義 1
1.1.1 現(xiàn)場可編程門陣列簡介 2
1.1.2 SRAM編程技術(shù)介紹 3
1.1.3 FPGA..
