目 錄

摘要 I

ABSTRACT II

1引言 1

2 2.5G HZ PLL鎖定檢測(cè)電路工作原理分析 2

2.1 鎖相環(huán)結(jié)構(gòu)簡(jiǎn)介 2
2.2 鎖相環(huán)的作用簡(jiǎn)介 2
2.3 鎖定檢測(cè) 3

3 2.5G HZ PLL鎖定檢測(cè)電路總體設(shè)計(jì)方案 5

3.1 概述 5
3.2 設(shè)計(jì)目標(biāo) 6
3.3 頂層設(shè)計(jì)方案 7
3.4 驗(yàn)證與測(cè)試 11

4 2.5G HZ PLL鎖定檢測(cè)電路反向提取分析 12

4.1 鎖定檢測(cè)電路外部引腳 12
4.2 鎖定檢測(cè)電路內(nèi)部結(jié)構(gòu) 13
4.3 鎖定檢測(cè)電路的實(shí)現(xiàn) 15
4.4 反向提取的鎖定檢測(cè)電路圖 16

5 2.5GHZ PLL鎖定檢測(cè)電路SMIC0.18工藝下重新設(shè)計(jì) 17

5.1 反相器設(shè)計(jì) 17
5.2 D觸發(fā)器設(shè)計(jì) 18
5.3 計(jì)數(shù)器設(shè)計(jì) 18
5.4 十八輸入或非門(mén)設(shè)計(jì) 19
5.5 與非門(mén)設(shè)計(jì) 20
5.6 時(shí)鐘設(shè)計(jì) 21
5.7 鎖定檢測(cè)電路設(shè)計(jì)小結(jié) 21

6 2.5G HZ PLL 鎖定檢測(cè)電路HSPICE 下晶體管級(jí)仿真 22

6.1 觸發(fā)器模塊仿真測(cè)試 22
6.2 異或門(mén)仿真測(cè)試 23
6.3 十八輸入或非門(mén)仿真測(cè)試 24
6.4 與非門(mén)仿真測(cè)試 25
6.5 鎖定檢測(cè)電路整體仿真測(cè)試 26

7 2.5G HZ PLL 鎖定檢測(cè)電路VERILOGHDL 語(yǔ)言描述 30

7.1 基本模塊的描述 30
7.2 鎖定檢測(cè)電路的整體描述 32

8 結(jié)論 33

致 謝 84

參考文獻(xiàn) 84

附錄：鎖定檢測(cè)電路的VERILOG硬件語(yǔ)言描述 84

摘 要

在集成電路設(shè)計(jì)中，需要使芯片上內(nèi)部時(shí)鐘和外部時(shí)鐘同步，希望在外部時(shí)鐘輸入的高頻率下使用芯片的內(nèi)部時(shí)鐘。基于以上兩點(diǎn)，鎖相環(huán)常常用于產(chǎn)生芯片上的內(nèi)時(shí)鐘。但是隨著處理器頻率的提高，傳統(tǒng)的數(shù)字鎖相環(huán)已經(jīng)不能滿(mǎn)足要求。在本文中，我們將展現(xiàn)一個(gè)新的鎖相環(huán)鎖定檢測(cè)方法。鎖定檢測(cè)的功能是檢測(cè)鎖相環(huán)是否達(dá)到鎖定。2.5G Hz PLL 鎖定檢測(cè)電路分析實(shí)現(xiàn)，就是要完成鎖定檢測(cè)電路的正向總體設(shè)計(jì)方案，鎖定檢測(cè)電路的反向提取，再在反向提取電路的基礎(chǔ)上在SMIC0.18 um 工藝下進(jìn)行重新設(shè)計(jì)，并完成HSPICE下的晶體管級(jí)仿真。2.5G Hz PLL 鎖定檢測(cè)電路分析實(shí)現(xiàn)的難點(diǎn)與重點(diǎn)是反向電路的提取和SMIC0.18 工藝下的重新設(shè)計(jì)。
本文所討論的鎖相環(huán)能夠鎖定更高頻率的時(shí)鐘。該鎖定檢測(cè)電路采用比較成熟的SMIC0.18 um工藝。鎖相環(huán)的壓控震蕩器的輸出頻率可以高達(dá)2.5GHZ。另外，該鎖相環(huán)能夠鎖定高達(dá)到2.5GHZ 的輸出頻率。我們采用模擬電路來(lái)代替以往的數(shù)字的鎖定檢測(cè)電路。在SMIC0.18 um工藝下，采用本文所討論的鎖定檢測(cè)電路而設(shè)計(jì)的鎖相環(huán)相對(duì)其他的鎖相環(huán)而言，具有更大的優(yōu)越性。

關(guān)鍵詞：鎖相環(huán) 鎖定檢測(cè) SMIC0.18um工藝 集成電路









Abstract

In integrated circuit design,we need to make the internal clock and the exterior clock of the chip synchronous, we also hope to use the internal clock of the chip under the high frequency clock of the exterior .According to the above , Phase-locked loops (PLLs) are usually used to create inside clock of the chip .But along with the exaltation of the processor frequency, the traditional digital PLL has already can't satisfy the request. In this paper, a new method of PLL lock detector will be presented. The function of the PLL lock detector is to test PLL whether attain to target or not. The analysis and realization of the 2.5 GHz PLL lock detector is to complete total design project, to complete the anti- to distill of circuit, base on the anti- to distill of the circuit and carry on re- designing in the process of SMIC0.18um, and complete the HSPICE simulation of the transistor class .The difficulty and importance of analysis and realization of circuit of 2.5 GHz PLL lock detector is the anti- to distill of the circuit and re-design under the process of SMIC0.18um.
The PLL this text discussed can target the clock which has a higher frequency. the lock detector circuit adoption the process of SMIC0.18um which is more mature now. The output of the VCO can be up to the 2.5 GHz. Moreover, the lock detector circuit is able to lock to form a 2.5 GHz output signal .We adoption the analog circuit instead of digital lock detector circuit. A PLL based on this type of lock detector demonstrated superior performance over other PLLs in this SMIC0.18um process.

Key Words: PLL,lock detector,SMIC0.18um, integrated circuit