鎖相環(huán)頻率合成器

全文52頁(yè) 約21000字 論述詳細(xì)

TD-SCDMA(時(shí)分雙工同步碼分多址)是我國(guó)提出的具有自主知識(shí)產(chǎn)權(quán)的第三代移動(dòng)通信空中接口標(biāo)準(zhǔn)，具有頻譜利用率高、支持多種通信接口、與傳統(tǒng)系統(tǒng)兼容性好、系統(tǒng)設(shè)備成本低和系統(tǒng)穩(wěn)定性好等特點(diǎn)。其中射頻收發(fā)信機(jī)是系統(tǒng)中的關(guān)鍵部件，從一定意義上決定了整個(gè)系統(tǒng)的通信質(zhì)量。隨著集成電路制造工藝和無(wú)線通信技術(shù)的迅速發(fā)展,實(shí)現(xiàn)全集成、多制式、低成本的無(wú)線收發(fā)器已成必然趨勢(shì)。頻率合成器作為無(wú)線收發(fā)器中的核心單元電路,是決定收發(fā)器性能好壞的關(guān)鍵因素,也是實(shí)現(xiàn)全集成無(wú)線收發(fā)器的主要難點(diǎn)。
本文系統(tǒng)地闡述了鎖相環(huán)頻率合成器的基本工作原理，較深入地分析了鎖相環(huán)路的組成和工作過(guò)程，建立其相位模型以及動(dòng)態(tài)方程，并且對(duì)環(huán)路的線性特性和噪聲特性進(jìn)行了詳細(xì)的分析。在此基礎(chǔ)上，針對(duì)TD-SCDMA系統(tǒng)的技術(shù)特點(diǎn)，以集成數(shù)字鎖相芯片為核心精心設(shè)計(jì)了頻率合成電路，構(gòu)成了多頻點(diǎn)輸出頻率合成器。本文對(duì)鎖相環(huán)路各個(gè)重要組成部分的參數(shù)進(jìn)行詳細(xì)的分析計(jì)算，仔細(xì)設(shè)計(jì)了原理圖。為了改善環(huán)路的捕獲性能，進(jìn)一步抑制鑒相器輸出電壓中的載頻分量和高頻噪聲，降低由VCO控制電壓的不純而引起的寄生輸出以及其他各種雜散噪聲，對(duì)環(huán)路濾波器進(jìn)行了重點(diǎn)設(shè)計(jì)，對(duì)多種方案進(jìn)行分析和比較，合理選擇和計(jì)算了環(huán)路的參數(shù)，進(jìn)而使得集成鎖相環(huán)頻率合成電路的功能得到了充分發(fā)揮，為T(mén)D-SCDMA系統(tǒng)提供了良好的本振源。最后我們給出了測(cè)試的方法以及測(cè)試結(jié)果。

關(guān)鍵詞：TD-SCDMA；鎖相環(huán)；頻率合成；VCO；環(huán)路濾波

ABSTRACT


TD-SCDMA (Time Division Synchronous CDMA)is one of the main flow Air Interface Criterions of 3G Communication Technology which is presented by China. TD-SCDMA has the noticeable advantages such as high一usage frequency spectrum, support various air interfaces, excellent compatibility with 2Gsystem, outstanding stability and the lower cost. Transceiver is the core component of the TD-SCDMA, to some extent, it plays the important role of the quality of the system. With the rapid development of IC (integrated circuits) fabrication processing and wireless communication technology, the implementation of a multi-standard, low-cost and fully integrated RF transceiver has become certainly the trend of development. The frequency synthesizer is a key building block in the RF transceiver. It is the determining factor of the overall performance of transceiver, and is also the biggest obstacle for its monolithic implementation.
This paper expatiates on foundational principles of the PLL-Frequency Synthesizer, analyzes the performance procedure and constitution of the PLL. In this paper, the author both builds the phase model and dynamic equation and studies the linear and noise characteristic of the PLL in detail. Via to the previous analysis, the model parameter and the property of TD-SCDMA system.
the author decides to adopt the transceiver scheme: Digital IF and one order conversion in analog. Moreover, the multiple frequency points output frequency synthesizer lies on the digital PLL IC. In the article, the author designs the schematic diagram. In order to improve loop acquisition, furthermore, reject higher-order harmonic and noise in the output voltage of the PD, reduce any other stray noises and parasitic component output which is due to impurity of control voltage by VCO. During the course of design process, on one hand, comparing and analyzing among the various design schemes, on the other hand, elaborately computing and selecting the parameters of the phase locked loop. Further more, it is obvious that the performance of the frequency synthesizer is enhanced distinctly. In addition, there is no denying that the outstanding local oscillator makes the system performance improved sharply. Finally, the simulation results and measurements of the whole circuit are displayed in the end of the article.
Key words: TD-SCDMA； PLL； VCO； Frequency Synthesizer,；Loop Filter

目 錄

1 緒論 ……………………………………………………………………………19
1.1、3G技術(shù)簡(jiǎn)介 ……………………………………………………………19
1.2 TD-SCDMA簡(jiǎn)介 …………………………………………………………20
1.3 本文的研究意義…………………………………………………………23

2 鎖相環(huán)的系統(tǒng)原理分析 ………………………………………………………24
2.1 鎖相環(huán)的基本組成………………………………………………………24
2.2 鎖相環(huán)的工作原理………………………………………………………25
2.3 泵鎖相環(huán)的基本組成 ……………………………………………………27
2.4 泵鎖相環(huán)的基本工作原理 ………………………………………………28
2.5 三階電荷泵鎖相環(huán)的穩(wěn)定性分析 ………………………………………28

3 頻率合成器設(shè)計(jì) ………………………………………………………………31
3.1 總體設(shè)計(jì) …………………………………………………………………31
3.2 鎖相環(huán)頻率合成器芯片原理圖設(shè)計(jì) ……………………………………33
3.3 芯片各部分功能介紹 ……………………………………………………35

4 系統(tǒng)的調(diào)試與測(cè)試 ……………………………………………………………44
4.1 調(diào)試注意的要點(diǎn) …………………………………………………………44
4.2 本振的測(cè)試及結(jié)果 ………………………………………………………45

5 總結(jié) ……………………………………………………………………………49

參考文獻(xiàn)……………………………………………………………………………
致謝…………………………………………………………………………………
附錄…………………………………………………………………………………

部分參考文獻(xiàn)

[23]張劍宇，孫承緩，來(lái)金梅，章倩荃.2. 4GHz頻率合成器可編程分頻器設(shè)計(jì)與實(shí)現(xiàn)
[24]復(fù)旦學(xué)報(bào)(自然科學(xué)版):2005(Vol. 44 No. 1) :140^143
[25]J. Parker, D. Ray. A low-noise 1. 6GHz CMOS PLL with on-chip loop filter.Proc. of the IEEE 1997 Cus七om Integrated Circuits Conference, SantaClara, USA. 1997:407^410
[26]S. M.Shahruz. Design of high-performance phase-locked loops and syn-thesizers. Journal of sound and vibra七ion. 2001(vol. 244 No. 2):367^377