摘 要
集成電路又稱為IC(Integrated Circuits)，是在硅板上集合多種電子元器件實現(xiàn)某種特定功能的電路模塊。它是電子設(shè)備中最重要的部分，承擔(dān)著運算和存儲的功能。集成電路的應(yīng)用范圍覆蓋了軍工、民用的幾乎所有的電子設(shè)備?？梢哉f集成電路是計算機(jī)業(yè)、數(shù)字家電業(yè)、通信等行業(yè)的絕對“心臟”。
隨著微電子技術(shù)的發(fā)展，集成電路的規(guī)模越來越大，結(jié)構(gòu)越來越復(fù)雜，集成電路的測試生成變得越來越難，花費的時間也越來越多。對于大規(guī)模的集成電路，傳統(tǒng)的測試生成算法已不再適用，尋找新型、有效的測試生成算法已成為一個重要的研究課題。
組合電路單固定型故障模型是國際上研究最早，也是采用最普遍的故障模型。實踐表明，只要單固定型故障的覆蓋率達(dá)到90%以上，那么單固定型故障的測試集也能檢測其它類型的故障，例如多故障和橋接故障。又因為系統(tǒng)在調(diào)試階段發(fā)生多故障的概率較大，但在使用階段發(fā)生單固定型故障的可能性要大得多，因此，單固定型故障的測試生成問題一直是國際上研究的熱點。從理論上講，單固定型故障的測試生成問題早在六十年代就己經(jīng)解決了。然而，理論分析證明，自動測試生成的時間復(fù)雜性是個NP完全問題。隨著電路規(guī)模的增大，測試生成越來越困難。因此，加速測試生成，提高測試生成效率一直為人們所關(guān)注。
本文采用單固定型故障模型，對組合電路的測試生成進(jìn)行了研究。以提高故障覆蓋率和減小測試生成時間為主要目標(biāo)，重點研究了以下內(nèi)容：
1．綜述了測試生成技術(shù)的研究現(xiàn)狀和發(fā)展概況。
2．研究了組合電路中非魯棒性路徑時滯故障的測試生成算法。
3．研究了組合電路基于搜索狀態(tài)控制的測試生成算法。
4．研究了組合電路多故障的測試生成算法。
關(guān)鍵詞 測試生成；固定型故障；時滯故障































Research of the Test Generation Algorithm for the Combinational Circuit
Abstract
Integrated circuit can be called IC for short, and it is a modular circuit that assembles multiple electronic components on the silicon board to fulfill some specific function. IC is the most important part in the electronic device, and it undertakes the functions of operating and storing. IC can be applied to almost all the electronic devices for civil use and military project. IC can be called the absolute “heart” for the computer, the digital domestic electricity, the communication and so on.
With the development of the microelectronic technique, the scale of the integrated circuits become more and more large, the structure become more and more complex, and the test generation for the integrated circuits is becoming increasingly difficult and time consuming. The traditional test generation algorithms are extremely inefficient for the large-scale circuits. Consequently, new and cost-effective algorithms are imperative research subjects today.
The single stuck-at fault model for combinational circuit is a fault model researched at the earliest internationally, and it is also the one used mostly. Practice shows that the test set for single stuck-at fault can test other kind fault, e.g. multi-fault and bridging fault, if only fault coverage for single stuck-at fault attains above 90%. Because the probability of happening multi-fault for system is big during debug phase and the possibility of happening single fault is bigger during usage phase, the test generation problem for single stuck-at fault is the hot spot of research internationally. On paper, it has solved earlier than 60 times. But theoretical analyze proofs that time complexity for automatic test generation is a NP-completeness problem. As the augment of circuit scale, test generation becomes more and more difficult. Therefore, accelerating test generation and improving its efficiency is noticed all along.
This paper uses the single stuck-at fault model and selects the combinational circuits as research targets. It mainly aims to improve the fault coverage and reduce the test generation time. The main contents are as following:
1. The development and current research status of the test generation is introduced in this paper.
2. The test generation algorithm for non-robust path delay fault in combination- al circuits is studied.
3. Test generation algorithm based on search state dominance for combinational circuits is studied.
4. A test generation algorithm in combinational circuits is studied.
Keywords test generation, stuck-at fault, delay fault























目錄
摘 要 I
Abstract III
第1章 緒論 1
1.1 測試生成算法的相關(guān)概念 2
1.1.1 測試生成的基本概念 .2
1.1.2 故障模型及模型化故障 3
1.2 測試生成算法概述 6
1.2.1 測試生成算法的研究現(xiàn)狀 6
1.2.2 測試生成的發(fā)展趨勢 8
1.3 課題的背景及研究內(nèi)容 9
1.3.1 課題的背景 9
1.3.2 課題的主要研究內(nèi)容 10
第2章 基于時滯故障的組合電路測試生成算法 11
2.1 時滯故障測試的基本知識 11
2.1.1 時滯故障模型 11
2.1.2 時滯測試的硬件模型 12
2.1.3 魯棒性測試與非魯棒性測試 13
2.2 基于固定型故障測試生成的時滯故障測試生成 14
2.2.1 基本知識 15
2.2.2 算法描述 17
2.2.3 實驗結(jié)果 19
2.3本章小結(jié) 19
第3章 基于狀態(tài)控制的組合電路測試生成算法 20
3.1 ..