共40頁，字數(shù)總計：16553
畢業(yè)設(shè)計：基于CPLD的頻率測量計
摘 要
本文提出了一種基于CPLD的數(shù)字頻率計的設(shè)計方法。復雜可編程邏輯器件（CPLD）具有集成度高、運算速度快、開發(fā)周期短等特點，它的出現(xiàn)，改變了數(shù)字電路的設(shè)計方法，增強了設(shè)計的靈活性。該設(shè)計電路簡潔，軟件潛力得到充分挖掘，低頻段測量精度高，有效防止了干擾的侵入。從實驗結(jié)果上看，采用CPLD設(shè)計的電子電路，可以彌補傳統(tǒng)硬件電子電路設(shè)計中的不足。該頻率計利用等精度的設(shè)計方法，克服了基于傳統(tǒng)測頻原理的頻率計的測量精度隨被測信號頻率的下降而降低的缺點。等精度的測量方法不但具有較高的測量精度，而且在整個頻率區(qū)域保持恒定的測試精度。該頻率計利用CPLD來實現(xiàn)頻率、周期、脈寬的測量計，完成整個測量電路的測試控制、數(shù)據(jù)處理和顯示輸出。并詳細論述了硬件電路的組成和軟件控制流程。其中硬件電路包括鍵控制模塊、顯示模塊、輸入信號整形模塊以及CPLD主控模塊。CPLD采用VHDL語言編寫，根據(jù)控制信號不同進行計數(shù)，并且輸出計數(shù)值到其接口中。本系統(tǒng)測量對象為方波、三角波、正弦波等等，測量范圍為1Hz-1MHz輸入信號經(jīng)過放大整形后接入CPLD電路。

關(guān)鍵詞：數(shù)字頻率計；CPLD；等精度
Abstract
This paper produces a CPLD-based digital frequency meter’s design method. complex programmable logic device (CPLD) has the of characteristics of highly integrated, high computing speed, shorter development cycle and so on, the appearance of it changes the methods of digital circuit design, and enhances design flexibility. this paper produces a CPLD-based digital frequency meter’s design method. This design’s circuit is simple, software’s potential is fully tapped and low-frequency measurements have high accuracy, effectively preventing the intrusion of the interference. The experimental results from the point of view, the use of CPLD design of electronic circuits can make up for the traditional hardware designing electronic. Circuit’s deficiencies. The use of such precision frequency meter design ways to overcome the traditional frequency measurement based on the principle of the measurement precision frequency meter with a decline in the measured signal frequency decreases the shortcomings. And other precision measurement method not only has high accuracy, but in the entire frequency region to maintain a constant precision. The frequency meter using CPLD to implement the frequency, period, pulse width and duty cycle measurement count.CPLD is written in VHDL language and counts according to different control signals translate from MCU part, finally, CPLD part will output the count result to the MCU part. The measured objects of the system are square wave, tri-angel wave, sine wave, etc., input signal is shaped after amplifying measurement ranges from 1Hz to 1MHz.

Keywords: Equal Precision; Frequency Meter; CPLD
目 錄
1 緒 論 1
1.1 本設(shè)計的目的和意義 1
1.2 頻率測量計國內(nèi)外現(xiàn)狀及發(fā)展趨勢 2
1.3 本設(shè)計要求 3
1.4 系統(tǒng)設(shè)計指標 3
2 方案論證 4
2.1頻率計結(jié)構(gòu)框圖 4
2.2測量方法論證 4
2.3 顯示部分的方案提出及比較 6
2.4 鍵盤部分的方案提出及比較 7
2.5 控制核心的方案提出及比較 8
3 硬件電路設(shè)計 12
3.1 頻率計的系統(tǒng)級總體結(jié)構(gòu)框圖 12
3.2 CPLD的芯片選擇 14
3.3 測量電路的設(shè)計 17
3.3.1 頻率的測量 18
3.3.2 脈沖寬度的測量 19
3.4 鍵盤部分的設(shè)計 20
3.5 顯示部分的設(shè)計 20
3.6 電源部分的設(shè)計 23
4 軟件電路的設(shè)計 24
4.1 主程序流程圖 24
4.2 VHDL程序設(shè)計 26
5 結(jié)論 29
致 謝 30
參考文獻 31