高速電路板級(jí)SI、PI與實(shí)踐



目  錄

一 論文正文

1緒論 1

  1.1 SI與PI基本原則 1

    1.2 信號(hào)完整性分析、電源完整性分析簡(jiǎn)介 2

2 SI的仿真與設(shè)計(jì) 3

    2.1 信號(hào)完整性分析定義與對(duì)象 3

    2.2 信號(hào)完整性問題 4

  2.3 SI的HyperLynx 仿真 13

3 PI仿真與設(shè)計(jì) 23

  3.1 概述 23

  3.2 電源系統(tǒng)的噪聲來源與電容的退耦 24

  3.3 PI的仿真分析 27

4總結(jié)與實(shí)例 32

參考文獻(xiàn) 34

謝辭 35

二 附錄

論文（設(shè)計(jì)）任務(wù)書 36

論文（設(shè)計(jì)）結(jié)題報(bào)告 38

論文（設(shè)計(jì)）成績(jī)?cè)u(píng)定及答辯評(píng)議表 40

論文（設(shè)計(jì)）答辯過程記錄 42

摘要：隨著PCB 設(shè)計(jì)越來越復(fù)雜，設(shè)計(jì)周期越來越短，信號(hào)完整性仿真分析正變得越來越重要。本文簡(jiǎn)介了信號(hào)完整性針對(duì)的基本問題，介紹了基于信號(hào)完整性仿真分析的高速PCB設(shè)計(jì)方法，并結(jié)合一個(gè)高速PCB 設(shè)計(jì)案例，通過Mentor Graphics公司電路系統(tǒng)仿真工具——HyperLynx，對(duì)高速板級(jí)電路進(jìn)行仿真。研究通過改變傳輸線參數(shù)、干擾源、地平面介質(zhì)對(duì)串?dāng)_的影響。根據(jù)PCB廠家的制版參數(shù)匹配出阻抗線。仿真分析出層間結(jié)構(gòu)、布局、布線規(guī)則和一些端接方案，完成仿真板級(jí)結(jié)果。

關(guān)鍵詞：信號(hào)完整性；信號(hào)完整性仿真 IBIS；串?dāng)_；傳輸線；HyperLynx仿真

High-speed circuit board level SI、PI and practice

Abstract: with the PCB design more and more complex, the design cycle more and more short, signal integrity simulation analysis is becoming more and more important. In this paper are introduced the signal integrity in the basic problem, introduces the simulation analysis based on signal integrity of the PCB design method, and combining with a high speed PCB design case, through the Mentor Graphics company circuit system simulation tools-HyperLynx, for high-speed circuit board level simulation. Research by changing the parameters of the transmission line, interference sources, ground plane media on the influence of crosstalk. According to the PCB manufacturer plate parameters matching the impedance line. The simulation analysis between the layer structure, layout and wiring rules and some termination program, complete simulation board level results.

Key words:Signal Integrity（SI ）;SI Simulation;IBIS;Crosstalk;transmission lines;HyperLynx simulation