掃描鏈阻塞技術(shù)中TSP的算法研究與實現(xiàn)
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摘 要

由于近二十年芯片密度快速增長，功耗成為大規(guī)模集成（VLSI）電路設(shè)計的最重要的因素之一。而且，數(shù)字系統(tǒng)的測試功耗被認(rèn)為要高于正常工作中的功耗。特別地，在掃描測試中，所有的掃描單元時鐘切換時所產(chǎn)生的大量能耗可能會燒毀芯片。因此，許多技術(shù)被用于最小化功耗或功耗限制下的測試。
測試功耗與被測電路的時鐘頻率和測試中晶體管的跳變數(shù)成正比，因此，降低時鐘頻率和晶體管的跳變數(shù)能降低測試功耗。掃描鏈阻塞技術(shù)能有效地降低測試功耗。在這種技術(shù)里，掃描鏈被分組成N個子掃描鏈。在某些時刻，僅有一個或者一部分掃描鏈?zhǔn)腔钴S的，從而電路的平均功耗和總功耗降低。我們在先前的文章里提出了一種新的方案，在這個方案里，在掃描測試的任意時刻（包括掃描移位周期和捕獲周期），僅有一個子掃描鏈活躍，電路的平均功耗，總功耗和峰值功耗都顯著降低。但對有些電路，這個方法的測試應(yīng)用時間增加。經(jīng)過初步研究，我們發(fā)現(xiàn)如果適當(dāng)調(diào)整測試向量的順序能顯著的降低測試應(yīng)用時間，求最小的測試應(yīng)用時間等價于TSP問題。實驗結(jié)果表明，我們的方法能有效地降低測試應(yīng)用時間。

關(guān)鍵詞：確定性測試，全掃描測試，掃描鏈阻塞，旅行商問題，低功耗測試

A Low Power Deterministic Test Using Scan Chain Disable Technique Based on a TSP Approach
Abstract
Due to the chip density increasing drastically through the last decade, power dissipation becomes one of the most important factors of very large scale integration design. Furthermore, power and energy consumption of digital systems are considerably higher in test mode than in normal mode. In particular, in the case of scan test, the power dissipation due to clocking all the scan flip-flops is so excessive that it may burn the chip .Hence, many techniques have investigated power minimization or power constrains test.
Test power dissipation depends directly on the global clock frequency and switching transitions of the circuit under test. Therefore, decreasing both the clock frequency and the switching activity can reduce test power. Scan chain disable technique can reduce test power efficiently. In the technique, the flip-flops are grouped into N scan chains. At sometime, just one scan chain or some of the scan chains are active. Average power is reduced. We previously proposed a low power deterministic test methodology. In this method, only a scan chain is active during both shift and capture cycles. Both peak power and average power are reduced drastically. However, the test application time of some benchmark circuits is increased. We find that if we reorder the test set, the test application time can be reduced. The problem to achieve shortest test application time is equivalent to a TSP problem. Experimental results show that our approach can efficiently reduce test application time.

Key Words: deterministic test, full scan testing, scan chain disable, traveling salesman problem, low power testing

目錄
1. 緒論 1
1.1本課題的目的和意義 1
1.2掃描鏈阻塞術(shù)技術(shù) 1
1.3文章的組織 2
2. 低功耗測試方案 4
2.1基本流程 4
2.2測試應(yīng)用時間的問題 5
3. 測試流程 7
4. 掃描單元和測試立方分組 9
4.1提出問題 9
4.2禁忌搜索算法 9
4.3掃描單元分組 11
4.4測試立方分組 12
5. TSP算法 14
5.1 TSP概念 14
5.2 TSP問題的基本性質(zhì) 14
5.3 LKH實現(xiàn) 15
6. TSP在阻塞掃描測試中的應(yīng)用 17
6.1 原方法的局限性 17
6.2 改進(jìn)的方法 18
6.3 LKH算法的應(yīng)用 18
6.4 實驗平臺 19
6.5 實驗步驟 19
7. 實驗結(jié)果與結(jié)論 21
總結(jié)與展望 22
致謝 23
參考文獻(xiàn) 24


參考文獻(xiàn)
[1] Y. Zorian, A distributed BIST control scheme for complex VLSI devices[A], Proc.IEEE VLSI Test symposium[C]
[2] P.Girad, Survey of low-power testing of LSI circuits[J], IEEE Des.Test comput
[3] K. Roy and S. Prasad,Low-power CMOS VLSI circuit design, John Wiley & sons
[4] H. Vranken, T. Waayers, H. Fleury, and D. Lelouvier, Enhanced reduced-pin-count test for full-scan處design[A], Proc. IEEE International Test Conference[C]
[5] S.Chakravarty and V.Dabholkar,Two techniques for minimizing power dissipation in scan circuits during test application[A]. Proc. IEEE Asian Test Symposium[C