Abstract— Many of the complex VLSI systems have separate I/O and core supplies and follow a predefined power up sequence. In this paper an on-chip power-on reset (POR) strategy and an I/O power supply detection circuit with low steady-state power consumption are proposed. Our technique allows the I/O power supply monitoring, independently from the core power supplies. The I/O power supply detection circuit can detect both ramp up and ramp dowvn of the supply oltage and has a fixed detection threshold. The circuit can operate for any I/O supply voltage level ranging from 1.5V to 3.3V. Simulation results show a maximum steady state power consumption of 23μW. Due to this fact the proposed POR circuit is suitable for low power applications and embedding in portable device systems.

摘要:超大規(guī)模集成電路系統(tǒng)有許多復(fù)雜單獨(dú)的I / O與核心供應(yīng)，并按照預(yù)定順序提供電源。在本文中推薦了復(fù)位片上電源（POR）和一個(gè)I / O電源低穩(wěn)態(tài)功率檢測(cè)電路耗能的方法。我們的技術(shù)允許I / O電源的電源監(jiān)控，獨(dú)立于內(nèi)核的電源供應(yīng)。該I / O電源檢測(cè)電路可以檢測(cè)兩個(gè)斜坡上升和下降的電源電壓和擁有一個(gè)固定的檢測(cè)閾值。該電路可以支持任何I/ O電源電壓水平范圍從1.5V到3.3V。模擬結(jié)果顯示，最大穩(wěn)態(tài)23μW功耗。由于這一點(diǎn)可知POR電路為低電源應(yīng)用，可適合于嵌入在便攜式設(shè)備系統(tǒng)。