基于vhdl的視頻圖像信號(hào)中的復(fù)合同步信號(hào)的產(chǎn)生.doc
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基于vhdl的視頻圖像信號(hào)中的復(fù)合同步信號(hào)的產(chǎn)生,基于vhdl的視頻圖像信號(hào)中的復(fù)合同步信號(hào)的產(chǎn)生全文約3000字 論述詳細(xì)摘要:視頻圖象復(fù)合同步信號(hào)由奇偶2場(1幀)重復(fù)組成,每場312.5行,由均衡脈沖、槽脈沖、行同步信號(hào)組成。本課題根據(jù)計(jì)數(shù)器的原理,利用vhdl作為設(shè)計(jì)的手段,在altera公司的quartus ii軟件環(huán)境下設(shè)計(jì)一個(gè)視頻圖像同步信號(hào)處理電路,以...
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基于VHDL的視頻圖像信號(hào)中的復(fù)合同步信號(hào)的產(chǎn)生
全文約3000字 論述詳細(xì)
摘要:
視頻圖象復(fù)合同步信號(hào)由奇偶2場(1幀)重復(fù)組成,每場312.5行,由均衡脈沖、槽脈沖、行同步信號(hào)組成。
本課題根據(jù)計(jì)數(shù)器的原理,利用VHDL作為設(shè)計(jì)的手段,在Altera公司的Quartus II軟件環(huán)境下設(shè)計(jì)一個(gè)視頻圖像同步信號(hào)處理電路,以完成視頻圖像信號(hào)中的復(fù)合同步信號(hào)的產(chǎn)生。
本文詳細(xì)論述了視頻圖像同步信號(hào)處理電路設(shè)計(jì)思路,具體的程序設(shè)計(jì)及程序仿真產(chǎn)生的波形信號(hào)。
關(guān)鍵詞:VHDL 視頻圖像復(fù)合同步信號(hào)
Abstract:
Video composite synchronization signals from parity 2 Course (1) of repeat, 312.5 per game trip which Balanced by the pulse, pulse groove, to sync signal components.
According to counter this topic Principle, Using VHDL design as a means of and In Altera's Quartus II software design environment of a video sync signal processing circuit, to complete the formation of composite sync signal.
This paper discusses in detail the video sync signal processing circuit design ideas, Specific procedures for the design and simulation procedures generated signal waveforms.
Key Word: VHDL Composite video sync signal
參考文獻(xiàn)
[1] 俞斯樂,電視原理,第六版,北京:國防工業(yè)出版社,2006.6
[2] 姜雪松 劉東升,硬件描述語言VHDL教程,西安:西安交通大學(xué)出版社,2004.1
全文約3000字 論述詳細(xì)
摘要:
視頻圖象復(fù)合同步信號(hào)由奇偶2場(1幀)重復(fù)組成,每場312.5行,由均衡脈沖、槽脈沖、行同步信號(hào)組成。
本課題根據(jù)計(jì)數(shù)器的原理,利用VHDL作為設(shè)計(jì)的手段,在Altera公司的Quartus II軟件環(huán)境下設(shè)計(jì)一個(gè)視頻圖像同步信號(hào)處理電路,以完成視頻圖像信號(hào)中的復(fù)合同步信號(hào)的產(chǎn)生。
本文詳細(xì)論述了視頻圖像同步信號(hào)處理電路設(shè)計(jì)思路,具體的程序設(shè)計(jì)及程序仿真產(chǎn)生的波形信號(hào)。
關(guān)鍵詞:VHDL 視頻圖像復(fù)合同步信號(hào)
Abstract:
Video composite synchronization signals from parity 2 Course (1) of repeat, 312.5 per game trip which Balanced by the pulse, pulse groove, to sync signal components.
According to counter this topic Principle, Using VHDL design as a means of and In Altera's Quartus II software design environment of a video sync signal processing circuit, to complete the formation of composite sync signal.
This paper discusses in detail the video sync signal processing circuit design ideas, Specific procedures for the design and simulation procedures generated signal waveforms.
Key Word: VHDL Composite video sync signal
參考文獻(xiàn)
[1] 俞斯樂,電視原理,第六版,北京:國防工業(yè)出版社,2006.6
[2] 姜雪松 劉東升,硬件描述語言VHDL教程,西安:西安交通大學(xué)出版社,2004.1
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