低速率語音編解碼專用芯片的設(shè)計

全文約4400字 論述翔實

　　文　摘　為了滿足可視電話系統(tǒng)對高質(zhì)量，低成本語音編解碼器的需要，采用數(shù)字信號處理器內(nèi)核(DSP Core)的方法，設(shè)計了符合ITU-T G.723.1建議的5.3kbit/s和6.3kbit/s雙速率語音編解碼器專用芯片。針對G.723.1算法特點，進(jìn)行算法優(yōu)化，如變卷積運算為加/減運算，避開求余運算等，并對需要最大運算量的情況作了模擬，保證語音編解碼器在最壞情況下也能正常工作。根據(jù)專用芯片的結(jié)構(gòu)，設(shè)計了編解碼器的流程和接口模塊，用較少的運算量和較小的存儲空間，實時實現(xiàn)了G.723.1建議及其附錄A的全部功能和選項，并通過了全套測試序列的檢驗，而且留出足夠多的資源實現(xiàn)自適應(yīng)回聲抵消、調(diào)制解調(diào)等其它功能。

　　關(guān)鍵詞　低速率語音編碼，專用芯片，可視電話

　　分類號　TN 912.3
ASIC design for low bit rate speech coding
JIA Zhike，CUI Huijuan，TANG Kun，F(xiàn)ENG Chongxi
Department of Electronic Engineering,Tsinghua University，Beijing 100084，China
　　Abstract　In order to get a high quality and low cost speech coder for videophone system，an ASIC (Application Specific Integrated Circuit) was designed using DSP core. The speech coder complies with ITU-T Recommendation G.723.1 (dual rate speech coder for multimedia communications transmitting at 5.3 & 6.3kbit/s). According to the features of the G.723.1 algorthm and the architecture of the ASIC，some optimizations were used to reduce the computation complex and the memory size. The worst case which would cost maximum computation amount was simulated to ensure the coder can work properly in this case. The chart of the coder and its performance were presented. There is still enough resource left in this ASIC to implement the MODEM and the echo cancellator.
　　Key words　low bit rate speech coding；　ASIC (Application Specific Integrated Circuit)； videophone

參考文獻(xiàn)
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　[2] ITU-T. Draft Recommendation G.723.1 Dual rate speech coder for multimedia telecommunications transmitting at 5.3 & 6.3 kbit/s. Ocotober，1995
　[3] ITU-T. Annex A to Recommendation G.723.1 Silence compression scheme for dual rate communications transmitting at 5.3 & 6.3 kbit/s. May，1996
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