Abstract
The SoPC (System on a Programmable Chip) aspects of the Stratix GX™ FPGA with 3.125Gbps SERDES are described. The FPGA was fabricated on a 0.13um, 9-layer
metal process. The 16 high-speed serial transceiver channels with Clock Data Recovery (CDR) provides 622-megabits per second (Mbps) to 3.125-Gbps full-duplex transceiver operation per channel. Another challenge described, is the implementation of 39 source-synchronous channels at 100Mbps to 1Gbps, utilizing Dynamic Phase Alignment (DPA). The implementation and integration of the FPGA logic array (with its own Hard IP) with the CDR and DPA channels involved grappling with SoC design
issues and methodologies.

摘要
帶有3.125Gbps 解串器的Stratix GX™ FPGA 的Sopc(可編程芯片)方面進(jìn)行了描述。
FPGA是虛構(gòu)的9層0.13um金屬的過程。16個帶時鐘數(shù)據(jù)恢復(fù)(CDR)的高速串行收發(fā)渠道提供622M每秒(Mbps)到每通道3.125-Gbps的全雙工收發(fā)器操作。另一個難題是對39個從100Mbps到1Gbps的同步源通道利用動態(tài)相位定位（DPA）的描述,FPGA邏輯陣列(有自己的固定IP)與CDR和DPA通道涉及克服SoC的設(shè)計問題和方法的實施和整合。