擴(kuò)展掃描樹結(jié)構(gòu)優(yōu)化中的一種低費(fèi)用方法(含開題+任務(wù)書)
1.3萬字 34頁


摘要
隨著超大規(guī)模集成技術(shù)的迅猛發(fā)展，集成電路的測試日益成為一個(gè)挑戰(zhàn)。測試生成的時(shí)間復(fù)雜性非常高。全掃描設(shè)計(jì)是最重要的可測試性設(shè)計(jì)方法之一，在這個(gè)方法中，全部觸發(fā)器都具有全可控性和全可觀察性。在測試模式下，所有觸發(fā)器在功能上形成一個(gè)或多個(gè)掃描鏈，各個(gè)掃描鏈通過掃描移位，所有觸發(fā)器都可被設(shè)置成任意期望的邏輯值。盡管全掃描測試可以徹底地降低測試生成的復(fù)雜性，但測試應(yīng)用時(shí)間太長，測試功耗過高，因此測試費(fèi)用非常高，降低測試費(fèi)用是數(shù)字電路測試中當(dāng)務(wù)之急要解決的問題之一。
掃描樹技術(shù)被提出用來減少測試應(yīng)用時(shí)間。在這些技術(shù)中，掃描單元被構(gòu)造成一個(gè)樹型結(jié)構(gòu)。對(duì)比單掃描鏈型結(jié)構(gòu)，電路中最長的掃描鏈的長度降低了，從而降低了測試數(shù)據(jù)量和測試應(yīng)用時(shí)間。在掃描操作中，經(jīng)過根掃描單元測試數(shù)據(jù)被掃描進(jìn)入掃描樹的每一個(gè)節(jié)點(diǎn)。掃描單元在掃描樹的同一級(jí)上有相同的測試數(shù)據(jù)。因此，為了保持故障覆蓋不變，同一級(jí)上的所有掃描單元對(duì)所有的測試向量相容。我們先前提出了一種擴(kuò)展相容性掃描樹結(jié)構(gòu)，這種技術(shù)通過添加邏輯非和異或函數(shù)擴(kuò)展了掃描單元的相容性，并對(duì)相容的掃描單元移入相同的測試向量值，大大降低了測試應(yīng)用時(shí)間和平均測試功耗。但這種技術(shù)的測試硬件開銷高，并且掃描輸出個(gè)數(shù)多，給測試響應(yīng)數(shù)據(jù)壓縮帶來了困難。
本文提出了一種基于啞元的擴(kuò)展相容性掃描樹構(gòu)造方法。此方法有效地降低了電路的掃描輸出個(gè)數(shù)。從而降低了測試響應(yīng)數(shù)據(jù)量，節(jié)省了許多數(shù)據(jù)壓縮的硬件，并為測試效率的提高帶來了潛在的好處。實(shí)驗(yàn)結(jié)果展示了我們的方法在保持改進(jìn)的擴(kuò)展相容性方法的優(yōu)點(diǎn)的同時(shí)，掃描輸出的個(gè)數(shù)比原始的擴(kuò)展相容性方法有顯著的降低，對(duì)于ISCAS’89的部分電路，掃描輸出的個(gè)數(shù)最大降低了48.3%。
關(guān)鍵字：可測性設(shè)計(jì)，全掃描測試，掃描樹，低功耗測試


A Low Cost Test for Extended Compatibilities Scan Tree Architecture ABSTRACT
With the transistor counts exponentially increasing, scan-based designs are widely employed to reduce test generation time. Full scan-based design is one of the most important designs for testability (DFT) methodologies in very large scale integration (VLSI) circuits and in system-on-chip (SoC) cores. In this DFT methodology, all flip-flops are enhanced to scan cells, and test application time depends on the length of the longest scan chain. Though full scan design reduces test generation complexity drastically, the test cost including test application time, test data volume and test power is very high, and it increases the cost of automatic test equipment (ATE).
Recently, scan tree techniques have been proposed to reduce test application time. In these techniques, scan cells are constructed into a tree structure. The length of the longest scan chain is reduced. During scan operation, test data are shifted into the scan tree via one scan cell at the root. The scan cells in the same level have the same shifted test data. Therefore, to keep fault coverage, the scan cells should be compatible for all the test vectors. We previously proposed an extended compatibilities scan tree technique, employing logic NOT and XOR functions, reduces test application time and average test power drastically by shifting the same test values into(out from) the compatible scan flip-flops simultaneously. However, the hardware overhead is higher. In particular, the number of scan outputs is too larger so that the compact of test response data is difficult.
This thesis proposes a scan tree architecture of extended compatibilities based on the concept of dumb element. This method can efficiently reduce the number of scan outputs. Experimental results show that our approach achieves almost the same test application time, test input data volume, test power and area overhead compared with the previous construction. For S38584 of ISCAS’89 benchmark circuits, the test response data volume reduces 48.3%.


Keywords：design for testability, full scan testing, scan tree, low power testing


目錄

摘要 I
ABSTRACT II
1緒論 1
1.1研究背景 1
1.2研究目標(biāo)及其內(nèi)容 3
1.2.1研究目標(biāo) 3
1.2.2研究內(nèi)容 4
1.3文章的組織 4
2.掃描樹結(jié)構(gòu) 5
2.1構(gòu)造掃描樹 5
3.擴(kuò)展掃描樹技術(shù) 7
3.1擴(kuò)展相容性的概念 7
3.2構(gòu)造掃描樹 8
3.3減少掃描輸出個(gè)數(shù) 9
3.4降低平均功耗 11
4擴(kuò)展相容性掃描樹的構(gòu)造方法 12
4.1相容圖 12
4.2原始擴(kuò)展相容性掃描樹構(gòu)造算法 12
4.3改進(jìn)的掃描樹構(gòu)造算法[28] 14
4.3.1掃描單元重新分組 15
4.3.2分組重新排序 16
4.3.3掃描樹倒置 16
4.3.4擴(kuò)展掃描樹的改進(jìn)算法 16
4.4此算法的缺點(diǎn) 17
5.基于啞元的擴(kuò)展相容性掃描樹構(gòu)造方法 18
5.1子節(jié)點(diǎn)的表示 18
5.1.1異或節(jié)點(diǎn)為其子節(jié)點(diǎn)的唯一前驅(qū)節(jié)點(diǎn) 18
5.1.2異或節(jié)點(diǎn)為其子節(jié)點(diǎn)的兩個(gè)前驅(qū)節(jié)點(diǎn)之一 18
5.2新的掃描樹構(gòu)造方法 19
6.平臺(tái)工具選擇及實(shí)驗(yàn)結(jié)果與結(jié)論 21
6.1平臺(tái)工具選擇 21
6.2實(shí)驗(yàn)結(jié)果 22
總結(jié)與展望 24
致謝 25
參考文獻(xiàn) 26



參考文獻(xiàn)
[25] B. B. Bhattacharya, S. C. Seth and S. Zhang, Double-tree scan: a novel low-power scan-path architecture[A], In Proc. IEEE International Test Conference[C], 2003:471-479.
[26] Z. You, M. Inoue, H. Fujiwara, Extended Compatibilities for Scan Tree Construction, Digest of papers, 11th IEEE European Test Symposium [C], 2006:13-18.
[27] 劉志華, 尤志強(qiáng), 張大方, 成永升, 擴(kuò)展相容性多掃描樹設(shè)計(jì)[J], 已投電子學(xué)報(bào).
[28] 成永升, 尤志強(qiáng), 鄺繼順, 基于擴(kuò)展相容性掃描樹結(jié)構(gòu)的低測試響應(yīng)數(shù)據(jù)量低布線難度方法[J], 已投電子學(xué)報(bào).
[29] 肖劍鋒, 尤志強(qiáng), 鄺繼順, 基于相容類加權(quán)的擴(kuò)展相容性掃描樹構(gòu)造算法[J], 半導(dǎo)體技術(shù)(已錄用).