孫祥龍   趙不賄   陳永   徐雷鈞

江蘇大學(xué)電氣信息工程學(xué)院，鎮(zhèn)江，江蘇，中國(guó)

 

摘  要：隨著物聯(lián)網(wǎng)、多媒體等技術(shù)的發(fā)展，復(fù)雜、高速數(shù)據(jù)傳輸與控制問(wèn)題突出。論文設(shè)計(jì)了一款基于FPGA的高效、通用的DMA引擎，用于PCIE與數(shù)據(jù)系統(tǒng)間的高速通訊接口。該引擎具有4路異步FIFO結(jié)構(gòu)的DMA上傳、4路DMA下傳數(shù)據(jù)通道，以及1路命令通道；命令優(yōu)先級(jí)最高，多數(shù)據(jù)通道同時(shí)使用時(shí)，采用Round_Robin仲裁方式，使各個(gè)DMA 通道處于同一優(yōu)先級(jí)。各通道可重配置，通過(guò)對(duì)通道配置打開(kāi)與否能夠減少通道輪詢帶來(lái)的系統(tǒng)資源消耗，提高系統(tǒng)的整體效率。經(jīng)測(cè)試，單通道上、下傳速率達(dá)到160MB/s，四通道上、下傳總速率達(dá)到155MB/s，該接口電路性能穩(wěn)定可靠，具有較好的推廣價(jià)值。

關(guān)鍵詞：通訊接口；控制器；FPGA；PCIE；DMA 

Design of PCIE DMA High-Speed Communication Interface based on FPGA

Xianglong Sun, Buhui Zhao , Yong Chen , Leijun Xu

School of Electrical and Information Engineering, Jiangsu University, Zhenjiang，Jiangsu，China

Abstract—With the development of internet of things and multimedia technology, the issues between control and high-speed data transmission become obvious. The paper designed a high-performance FPGA-based, general-purpose DMA engine  for high-speed communication interface between PCIE and data system. The engine has four DMA upstream channels and four DMA downstream channels with asynchronous FIFO, as well as a command channel; The priority for commanding is the highest, the circuit uses Round_Robin arbitration to ensure each DMA channel at the same priority level when multiple data channels work simultaneously. Each channel can be re-configured to make the channel open or not, which can reduce the channel polling resource consumption and improve the overall efficiency of the system. From the test ,the speed of a single channel upstream or downstream can reach to 160MB/s; the speeds of four channels with upstream or downstream can reach to 155MB/s. The interface is stable and reliable, it has good popularized value.

Key words—Communication interface ; Controller ; FPGA ; PCIE ; DMA