Introduction
The use of hardware description language (HDL) is becoming a more dominant factor, when designing and verifying FPGA designs. The use of behavior level description not only increases the design productivity, but also provides unique advantages in the design verification. The most dominant HDL stoday are called Verilog and VHDL. This application note will illustrate the use of Verilog in design and verification of a digital UART (Universal Asynchronous Receiver & Transmitter).



簡介
使用硬件描述語言 (HDL) 設計和開發(fā)驗證FPGA的成為當前的主流因素。使用行為級描述不只增加了產(chǎn)品的設計效率，也在設計中有獨特的驗證方式。目前最流行的HDL語言為Verilog 和 VHDL。 這篇文章將會舉例說明用 Verilog語言 的設計和驗證數(shù)字異步串行收發(fā)器UART。